Conventionally, various driving method which are applied to an image display device such as a liquid crystal display device have been suggested and put to practical use. What is particularly researched and developed is an active matrix driving method. This method is suitable for graphics display, and is being researched and developed enthusiastically.
As shown in FIG. 52, a liquid crystal display device adopting the active matrix driving method is provided with a picture element array 101, a data signal line driving circuit 102 and a scanning signal line driving circuit 103. The picture element array 101 has a plurality of data signal lines SL and a plurality of scanning signal lines GL which cross one another. A picture element 104 is provided to a portion which is surrounded by the two adjacent data signal lines SL and two adjacent scanning signal lines GL, and the picture elements 104 are arranged over the entire part of the picture element array 101 in a matrix pattern.
The data signal line driving circuit 102 samples an inputted video signal DAT in synchronization with a timing signal such as a clock CKS within one horizontal scanning period and amplifies the sampled signal if necessary so as to write it to each data signa line SL. The signal to be written corresponds to gradation representing a luminance level of an image to be displayed. When the scanning signal line driving circuit 103 successively selects the scanning signal lines GL in synchronization with a timing signal such as a clock CKG per horizontal scanning period, the scanning signal line driving circuit 103 controls an on/off operation of a switching element (for example, thin film transistor), not shown, in the picture element 104. As a result, the video signal (data) written to each data signal line SL is written to each picture element 104, and the written data are retained.
In the conventional active matrix-type liquid crystal display device, the switching element, i.e. a picture element transistor is generally composed of an amorphous silicon thin film formed on a transparent substrate. Moreover, circuits such as the data signal line driving circuit 102 and the scanning signal line driving circuit 103 are composed of IC which is installed from the outside.
On the contrary, in recent years, according to demands for improvement in driving force of the picture element transistor, lowering of mounting cost of a driving IC, reliability in mounting, etc. to accompany the increase in size of a screen, a technique that the picture element array 101 and the driving circuits 102 and 103 are formed monolithically by using a polycrystal silicon thin film is reported. Moreover, in order to attain the further increase in size of a screen and a lower price, an element is tried to be formed by using an polycrystal silicon thin film on a glass substrate at a processing temperature not higher than a distortion point of glass (about 600.degree. C.).
The following describes a method of writing a video signal to the data signal line SL in such a liquid crystal display device. As the driving method of the data signal line SL, there exists an analog method and a digital method.
In the conventional analog-type data signal line driving circuit, as shown in FIG. 53, a shift register 120 is rest in synchronization with a start pulse SPS which is created based upon a horizontal synchronizing signal, etc. contained in an analog video signal DAT. As a result, a sampling signal is successively outputted to gates of analog switches TR in synchronization with a clock CSK having approximately a period obtained by dividing one horizontal scanning period by a number of channels of the data signal lines SL.
A video signal DAT is inputted commonly to sources of the analog switches TR from an video signal source, not shown. The video signal DAT is successively sampled by the analog switches TR and held by hold capacitors C so as to be applied to the data signal lines SL as a gradation signal.
At this time, in the picture elements 104 connected to the scanning signal lines GL selected by the scanning signal line driving circuit 103, the switching element SW is turned on. As a result, the gradation signal applied to the data signal lines SL in the above manner is written to a picture element capacity C.sub.P through the switching element SW. The written gradation signal is held until next sampling time, and thus an image is displayed.
In the analog-type data signal line driving circuit, in order to obtain a display image with high resolution and high definition for display of a high-definition television image and computer image, horizontal resolution should be increased by increasing a number of the data signal lines. However, when a number of the data signal lines is increased, there arises such a problem that defective writing of the gradation signal to the picture element capacity occurs.
For example, in the case of VGA (Video Graphics Array) method, since one horizontal scanning period (1H) is 1/(480.times.60).apprxeq.30 .mu.sec, if horizontal resolution is 640 lines, a period T.sub.on1 of turning ON the analog switches TR becomes 46 .mu.sec according to the following equation: EQU T.sub.on1 =30.times.10.sup.-6 /640=46 (n sec)
On the contrary, since a time T.sub.s1 required for writing the gradation signal to the picture element capacity C.sub.P accurately (not less than 99%) is required at least 5 times longer than time constant, if a capacity value of the picture element capacity C.sub.P is 20 pF and conduction resistance of the analog switches TR is 1 k.OMEGA., the time T.sub.s1 is calculated according to the following equation: EQU T.sub.s1 =20.times.10.sup.-9 .times.1.times.10.sup.3 .times.5=100 (n sec)
In the above-mentioned data signal line driving circuit, since the period T.sub.on1 as a sampling period is so short with respect to the time T.sub.s1 that the gradation signal cannot be written to the picture element capacity C.sub.P accurately.
Meanwhile, in the conventional digital-type data signal line driving circuit, as shown in FIG. 54, when a scanning signal SCAN is inputted, a sampling pulse is outputted from the scanning circuit 105 in time series. The video data DAT are sampled by a sampling circuit 106 in synchronization with the sampling pulse.
After the sampled n-bit digital signal is retained by a latch 107, it is transferred in synchronization with a transfer signal TF in next horizontal scanning period, and it is decoded by a decoder 108. As to a plurality of switching transistors, not shown, composing an output switch 109, their on/off operation is controlled by the decoded signal from the decoder 108. When one of the switching transistors is turned on, one of the 2.sup.n gradation power source lines is selected, and the selected gradation power source line is connected to the data signal line SL.
The above data signal line driving circuit can display a 2.sup.n -gradation image, but since the same number of gradation power source lines as a number of gradations are required, multi-gradation display is limited in a practical use, so 8-gradation or not more than 16-gradation image is usually displayed.
In a data signal line driving circuit shown in FIG. 55, a digital signal sampled by the sampling circuit 106 is divided into m-bit and h-bit. The respective signals are converted into 2.sup.m -numbered decoded signals and 2.sup.h -numbered decoded signals through latches 110 and the decoders 111. 2.sup.m -numbered decoded signals are applied to the output switch 109 in order to select two of 2.sup.m +1 gradation power source lines. The 2.sup.h decoded signals are applied to a medial value generator 112 for generating a medial value of two voltages outputted from the output switch 109.
As to the medial value generator 112, a plurality of resistors are connected in a series between adjacent gradation power source lines, and the medial value generator 112 is a circuit for generating a medial value by dividing of the resistor. For example, such a circuit is suggested in SID '94 DIGEST P. 351-354. Moreover, in the data signal line driving circuit, as to the medial value generator 112, a number of gradation power source lines is decreased to about 1/8 of a number of gradations (9 power source lines for 64-gradation display) by selecting two gradation power source lines by the output switch 109.
In addition, another arrangement for decreasing a number of gradation power source lines is a digital driver using a vibrating voltage as shown in FIG. 56. As suggested in SID '93 DIGEST p. 11-14, this uses a signal which vibrates between two voltages V.sub.cc and V.sub.ss, and according to its duty ratio, a halftone image can be displayed. In example in FIG. 56, voltages V.sub.1 through V.sub.8 for 8 gradations are outputted according to the two voltages V.sub.cc and V.sub.ss, but if this method is expanded, similarly to the data signal line driving circuit shown in FIG. 55, 64-gradation display becomes possible by using the 9 gradation power source lines.
In addition, another method, as shown in FIG. 57, is a driving method such that by inputting a ramp voltage V.sub.R whose level changes in a range of low level to high level like staircase to one power source line, the voltage of the power source line is taken in at timing (gradation basic signals F.sub.1 through F.sub.n) corresponding to display data (see Japanese Examined Patent Publication No. 7-50389/1995 (Tokukohei 7-50389)). With this method, theoretically, an image with any number of gradations can be displayed by using only one power source line.
In the case where the aforementioned elements (transistor, resistor, etc.) composed of a polycrystal silicon thin film are produced on a glass substrate, since a grain diameter of silicon crystal becomes large, the grain diameter and the size of the elements becomes approximately the same. Therefore, elements composed of a polycrystal silicon thin film has such a disadvantage that scattering of properties is unavoidable unlike elements formed on a monocrystal silicon substrate.
When the resistance divider of the medial value generator 112 are arranged by using such elements, dispersion occurs in values of the respective resistors. For this reason, in a data signal line driving circuit having the medial value generator 112, it is difficult to obtain a high-accurate medial value, an increase in a number of gradations is limited. For example, in the data signal line driving circuit shown in FIG. 55, when the increase in a number of gradations in a practical use is permitted to 4 times by the resistance divider, the maximum number of gradations to be displayed by combinations of 9 gradation voltages is 32 gradations, so this arrangement is not suitable for high gradation display.
In addition, in the polycrystal silicon thin film transistor, its driving force (mobility of carrier) is dozens times to several hundred times larger than the amorphous silicon thin film transistor. For this reason, in the case where the polycrystal silicon thin film transistor is used as a picture element transistor, if a bus line (data signal line) and the picture element transistor are regarded as a low pass filter, a cut-off frequency of the low pass filter becomes high. Therefore, when a halftone image is displayed according to the aforementioned vibrating signal by using such elements, an integration of the vibrating signal becomes insufficient. As a result, it might be impossible to achieve gradation display.
In addition, as disclosed in Japanese Examined Patent Publication No. 7-50389/1995 (Tokukohei 7-50389), in the driving method using only one power source line to which a ramp voltage is applied, a number of power source lines is one, but a given time for taking-in of a gradation signal is one fraction of a number of gradations for a horizontal scanning period. For this reason, a number of display gradations is actually limited by time constant of a data signal line (particularly a load capacity).
The following details the driving circuit disclosed in Japanese Examined Patent Publication No. 7-50389/1995 (Tokukohei 7-50389) on reference to FIGS. 58 and 59. Here, for convenience of explanation, those members that have the same arrangement and functions as the data signal line driving circuit shown in FIG. 53 are indicated by the same reference numerals. n-bit digital video data DAT are inputted to the driving circuit, and this video data DAT are applied commonly to a plurality of latch cells composing a latch 121. Each latch cell latches the video data DAT in synchronization with a sampling signal from each output terminal of the shift register 120. As a result, the video data DAT are successively stored in each latch cell according to the sampling signal which are successively outputted in a horizontal scanning direction.
The signals respectively stored in the latch cells are outputted to latch cells composing a latch 122. In the latch 122, the data respectively stored in the latch cell of the latch 121 are simultaneously latched in synchronization with a transfer signal TF and retained until next transfer signal TF is inputted. The data stored in the latch 122 are transferred to a comparing circuit 123. An n-bit gradation reference signal GR, which corresponds to the range of off-level to on-level of liquid crystal and changes periodically, is inputted commonly to comparator cells composing the comparing circuit 123.
The above-mentioned respective comparator cells output sampling signals to gates of the corresponding analog switches TR only for a period that the data from the latch 122 coincide with bit signals GR.sub.1 through GR.sub.n composing the gradation reference signal GR shown in FIG. 59, namely, for a period T.sub.on which is given to one gradation level of the gradation voltage GV. Meanwhile, the gradation voltage GV whose amplitude level changes periodically in synchronization with the gradation reference signal GR is inputted commonly to the sources of the analog switches TR. As a result, a voltage corresponding to luminance level of an analog video signal which is a base of the video data DAT is outputted from the analog switches TR through the hold capacitors C to the data signal lines SL.
As shown in FIG. 59, the gradation voltage GV changes at a step corresponding to 2.sup.n gradation for one horizontal scanning period (1H) in the range of the minimum level to the maximum level. Moreover, the gradation voltage GV and the gradation reference signal GR are rest in synchronization with a start pulse SP.
In the above driving circuit, a sampling period T.sub.on2 of the data signal lines SL becomes 1H/2.sup.n according to one horizontal scanning period (1H) and a number of gradations 2.sup.n. However, since a video signal does not actually exists during all the one horizontal scanning periods, the sampling period T.sub.on2 becomes shorter.
As mentioned above, when a conduction resistance of the analog switch TR is 1 k.OMEGA. and a capacity value of the picture element capacity C.sub.P is 20 pF, a time T.sub.s2 required for writing the gradation voltage GV to the picture element capacity C.sub.P is 100 n sec which is the same as the time T.sub.s1. On the contrary, in the case of the VGA mode, since one horizontal scanning period is 30.mu. sec as mentioned above, when a number of display gradations is 256, the sampling period T.sub.on2 is calculated according to the following formula: EQU T.sub.on2 =30.times.10.sup.-6 /256=117 (n sec)
As described above, in the above driving circuit, since the sampling period T.sub.on2 is longer than the time T.sub.s2, the gradation voltage GV can be written to the picture element capacity C.sub.P accurately, 256-gradation display by the VGA mode can be realized.
In the data signal line driving circuit 102 shown in FIG. 53, a time obtained by dividing one horizontal scanning period by a number of picture elements per one line was the sampling period. On the contrary, in the driving circuit shown in FIG. 58, a time obtained by dividing one horizontal scanning period by a number of gradations was the sampling period, thereby realizing high resolution and high definition.
However, in the case where a number of gradations is such a fairly large value as 512 gradations, since the sampling period T.sub.on2 is 59 n sec, the sampling period T.sub.on2 becomes shorter than the time T.sub.s2. For this reason, in the case of high gradation, the gradation voltage GV cannot be written to the picture element capacity C.sub.P accurately even by the driving circuit shown in FIG. 58.
The following describes mounting of the above driving circuit. As shown in FIG. 60, a driving circuit 131 which is provided as an integrated circuit is mounted on a side of a display section 132 on an insulating substrate (not shown). More concretely, data signal lines SL formed on the insulating substrate and output terminals 133 of the driving circuit 131 are electrically connected one another by soldering through a contact pads 134 provided on the ends of the data signal lines SL.
A width of the contact pad 134 is wider than the data signal lines SL so as to have allowance for displacement of the driving circuit 131. Therefore, wiring intervals of the data signal lines SL should be secured according to the width of the contact pad 134. However, if there exists such a limitation on the wiring intervals, the wiring intervals of the data signal lines SL cannot be made small, so it is difficult to improve resolution.
In order to remove the above defectiveness, a driving circuit 135 shown in FIG. 61 is considered to be used. The driving circuit 135 has output terminals arranged in two different rows alternately. Contact pads 136 provided on the ends of the odd numbered data signal lines SL.sub.1, SL.sub.3, . . . are arranged on a side which is closer to a display section 132 on the driving circuit 135. Contact pads 137 provided on the ends of the even numbered data signal lines SL.sub.2, SL.sub.4, . . . are arranged on a side which is farther from the display section 132 on the driving circuit 135.
As shown in FIG. 62 which is enlarged drawing of a J section in FIG. 61, the contact pads 137 have a width W.sub.1, and the data signal lines SL have a width W.sub.2 which is narrower than W.sub.1. Therefore, when the data signal lines SL are arranged respectively between the adjacent contact pads 136, the limitation on the wiring intervals due to the width W.sub.1 is eased. As a result, the high resolution can be realized by making the intervals of the data signal lines SL narrower.
However, since a width W.sub.3 between the contact pads 136 cannot be made narrower than the width W.sub.2, it is impossible to further improve the resolution.
Furthermore, the following describes power consumption of the above-mentioned driving circuit. For example, in the analog switches TR composed of the n-channel-type field effect transistors, a relationship shown in FIG. 63 is fulfilled between a gate-source voltage V.sub.gs and a drain current I.sub.d. In order to sufficiently apply the drain current I.sub.d (gradation signal), an electric potential V.sub.g of a gate electrode should have a value obtained by adding a threshold value voltage V.sub.th required for conduction of the analog switches TR and allowance a to an electric potential V.sub.s of a source electrode.
For this reason, as shown in FIG. 64, when the value of an amplitude of the gradation voltage GV is V.sub.amp, an amplitude V.sub.a of a sampling signal should be at least V.sub.amp +Vth+.alpha.. Namely, the sampling signal to the analog switches TR should have a larger voltage than a voltage to be applied to the picture element capacity C.sub.P through the data signal lines SL. Therefore, it is impossible to lower a driving voltage, which meets demands for lower power consumption.
In addition, in order to realize the lower power consumption, as shown in FIG. 59, it is considered that the dynamic range V.sub.dyn of the gradation voltage GV is made small. As the dynamic range V.sub.dyn corresponds to the range of off-level to on-level, the dynamic range V.sub.dyn of the gradation voltage GV can be small by using liquid crystal with small dynamic range V.sub.dyn.
However, in the case of 512 gradations, when the dynamic range V.sub.dyn is 5V, variations .DELTA.V of the gradation voltage GV per one gradation becomes not more than 10 mV. Such control of the very small gradation voltage GV is difficult, and is not practical.
In addition, in order to lower power consumption, as shown in FIG. 65, a method of dividing the data signal line driving circuits into a first block 141 through a third block 143 has been used.
As shown in FIG. 66, power source voltages BV.sub.1 through BV.sub.3 and clocks BCK.sub.1 through BCK.sub.3 are successively applied to the first through third blocks 141 through 143 according to horizontal scanning per about 1/3 period of one horizontal scanning period (1H). Therefore, the first through third blocks 141 through 143 are actuated only for about 1/3 period of 1H, and they stops for remaining 2/3 period. When the data signal line driving circuit is driven dividedly, as mentioned above, the power consumption can be reduced to about 1/3.
However, even if the above method is applied to the data signal line driving circuit 102 shown in FIG. 58, the sections other than the shift register 120 are actuated for most of the period. For this reason, it is necessary to always supply the power source and the clock CSK to the sections other than the shift register 120, a decrease in the power consumption cannot be expected much.